Transmission and reception stream processing devices for processing stream coded with coding rate of 1/3, and methods thereof

ABSTRACT

An apparatus for processing a transport stream is provided. The apparatus includes a detector which detects data bits in a stream, an encoder which encodes the data bits detected by the detector and generates two encoding values for each data bit, and a stream constructor which constructs a transport stream using the encoding values generated by the encoder. Accordingly, it is possible to encode the data bits into a transport stream having a coding rate of ⅓.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a National Stage of International Application No.PCT/KR2007/002952 filed Jun. 18, 2007 and claims benefit of U.S.Provisional Application No. 60/814,070 filed on Jun. 16, 2006, thedisclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Devices and methods consistent with the present invention relate toprocessing transmitted and received streams, and more particularly, toprocessing transmission and reception streams, in which streams coded ata coding rate of ⅓ are transmitted or received and the transmitted orreceived streams are processed.

2. Description of the Related Art

With the development of electronic and communication technologies,digital technologies have been introduced into the field of broadcastingsystem, and diverse standards for digital broadcasting have beenpublished. Specifically, examples of such standards are U.S.-orientedAdvanced Television Systems Committee (ATSC) Vestigial Side Band (VSB)standard, and European-oriented Digital Video Broadcasting forTerrestrial Television (DVB-T) system. These two standards vary fromeach other in many ways, such as ways of audio compression, channelbands, number of carrier waves, etc.

The U.S-oriented digital broadcasting (8-VSB) system defines that a VSBdata frame includes two fields, and one field includes one field syncsegment, which is the first segment, and 312 other data segments. Also,one segment in the VSB data frame corresponds to one MPEG-2 packet, andis composed of a segment sync signal of four symbols and 828 datasymbols.

The U.S.-oriented digital broadcasting system conforms to the ATSC DTVstandard. Recently, attempts have been made to generate andtransmit/receive a multi-stream by adding robust-processed turbo codingdata to normal data of the conventional ATSC VSB system.

In this situation, the turbo coding data transmitted together with thenormal data may be data, which is coded at a coding rate different fromthe normal data to have robustness different from the normal data.Accordingly, various types of data may be transmitted together in asingle frame, and thus broadcasts may be appropriately provided tovarious types of digital broadcasting apparatuses.

In order to generate such various types of data, various coding ratesneed to be applied. However, since there is no configuration to code andtransmit a stream at a coding rate of ⅓ in the conventional art, it isdifficult to generate various types of data.

SUMMARY OF THE INVENTION

An aspect of the present invention is to provide transmission/receptionprocessing devices and methods thereof which can process various typesof data by transmitting or receiving a stream coded at a coding rate of⅓.

According to an aspect of the present invention, there is provided atransmission stream processing device comprising a detector to detectdata bits from a stream; an encoder to encode the detected data bits andgenerate two encoding values for each data bit; and a stream constructorto construct a transmission stream with a coding rate of ⅓ using thegenerated encoding values.

The encoder may comprise first, second and third shift registers whichare connected in series to perform shifting operations complementary toeach other; a bit output line to output a data bit value withoutalteration if the data bit in the stream is input; a first adder to sumthe data bit value output from the bit output line, a value prestored inthe first shift register and a value prestored in the third shiftregister, and to output the sum of the values to the third shiftregister; a second adder to sum the data bit value output from the bitoutput line, a value prestored in the second shift register and a valueprestored in the third shift register, and to output the sum of thevalues as a first encoding value for the data bit value; and a thirdadder to sum the data bit value output from the bit output line and thevalue prestored in the second shift register, and to output the sum ofthe values as a second encoding value for the data bit value.

Accordingly, the stream constructor may sequentially arrange the databit value, first encoding value and second encoding value which areoutput from the encoder, to construct the transmission stream.

The device may further comprise a duplicator to receive the stream andgenerate place-holders at one side of each of the data bits in thestream.

In this situation, the encoder may comprise first, second and thirdshift registers which are connected in series to perform shiftingoperations complementary to each other; a first adder to sum a data bitvalue, a value prestored in the first shift register and a valueprestored in the third shift register, and to output the sum of thevalues to the third shift register if the data bit in the stream isinput; a second adder to sum the data bit value, a value prestored inthe second shift register and a value prestored in the third shiftregister, and to output the sum of the values as a first encoding valuefor the data bit value; and a third adder to sum the data bit value andthe value prestored in the second shift register, and to output the sumof the values as a second encoding value for the data bit value.

The stream constructor may construct the transmission stream byinserting the first and second encoding values output for each data bitin the place-holders.

According to an aspect of the present invention, there is provided atransmission stream processing method comprising detecting data bitsfrom a stream; encoding the detected data bits to generate two encodingvalues for each data bit; and constructing a transmission stream with acoding rate of ⅓ using the encoding values.

The encoding may comprise encoding each of the data bits using anencoder comprising first, second and third shift registers, which areconnected in series to perform shifting operations complementary to eachother, and a plurality of adders, and outputting data bit values and thetwo encoding values for each data bit.

The constructing may comprise sequentially arranging the data bit value,first encoding value and second encoding value which are output from theencoder, to construct the transmission stream.

The method may further comprise receiving the stream and generatingplaceholders on one side of each of the data bits in the stream. Thedetecting may comprise detecting the data bits from the stream havingthe place-holders.

The encoding may comprise encoding each of the data bits using anencoder comprising first, second and third shift registers, which areconnected in series to perform shifting operations complementary to eachother, and a plurality of adders, and outputting two encoding values foreach data bit.

The constructing may comprise constructing the transmission stream byinserting the two encoding values output from the encoder into theplace-holders.

According to an aspect of the present invention, there is provided areception stream processing device comprising a receiver to receive astream coded at a coding rate of ⅓; a detector to detect data bits andencoding values in the stream; and a decoder to perform decoding usingthe detected data bits and encoding values to retrieve data in thestream.

According to another aspect of the present invention, there is provideda reception stream processing method comprising receiving a stream codedat a coding rate of ⅓; detecting data bits and encoding values in thestream; and performing decoding using the detected data bits andencoding values to retrieve data in the stream.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and/or other aspects of the invention will become and morereadily appreciated from the following description of the exemplaryembodiments, taken in conjunction with the accompanying drawings ofwhich:

FIG. 1 is a block diagram showing a configuration of a transmissionstream processing device according to an exemplary embodiment of thepresent invention;

FIG. 2 is a circuit diagram showing a configuration of an encoder whichis applied to the transmission stream processing device of FIG. 1according to an exemplary embodiment of the present invention;

FIG. 3 is an exemplary diagram explaining a stream processing method inthe transmission stream processing device of FIG. 1 according to anexemplary embodiment of the present invention;

FIG. 4 is a block diagram showing a configuration of a transmissionstream processing device according to another exemplary embodiment ofthe present invention;

FIG. 5 is a circuit diagram showing a configuration of an encoder whichis applied to the transmission stream processing device of FIG. 4according to an exemplary embodiment of the present invention;

FIG. 6 is an exemplary view explaining a stream processing method in thetransmission stream processing device of FIG. 4;

FIG. 7 is a block diagram showing a configuration of a reception streamprocessing device according to an exemplary embodiment of the presentinvention; and

FIG. 8 is a flowchart explaining a reception stream processing methodaccording to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Reference will now be made in detail to the exemplary embodiments of thepresent invention, examples of which are illustrated in the accompanyingdrawings, wherein like reference numerals refer to the like elementsthroughout. The exemplary embodiments are described below in order toexplain the present invention by referring to the figures.

FIG. 1 is a block diagram showing a configuration of a transmissionstream processing device according to an exemplary embodiment of thepresent invention. The transmission stream processing device of FIG. 1comprises a detector 110, an encoder 120 and a stream constructor 130.

The detector 110 detects data bits from a stream to be transmitted, andoutputs the detected data bits to the encoder 120. The detector 110 maydetect data bits from the stream in reverse order, and output thedetected data bits to the encoder 120. For example, if data bits DO, D1,D2, D3, D4, D5, D6 and D7 of the stream are sequentially input in thestream, the detector 110 may detect the data bits from the stream in theorder of D7, D6, D5, D4, D3, D2, D1 and DO and output the detected databits to the encoder 120 in the order detected.

The encoder 120 encodes the detected data bits and generates twoencoding values for each data bit. The encoder may output each data bittogether with the encoding values.

The stream constructor 130 constructs a stream using the generatedencoding values output by the encoder 120. As a result, a stream codedwith a coding rate of ⅓ may be generated. In other words, single bytedata is coded to obtain a stream of three bytes.

FIG. 2 is a circuit diagram showing a detailed configuration of theencoder 120 which is applied to the transmission stream processingdevice of FIG. 1 according to an exemplary embodiment of the presentinvention. In FIG. 2, the encoder 120 comprises a bit output line 121, aplurality of shift registers SO, S1 and S2, and a plurality of adders122, 123 and 124.

The bit output line 121 is a line which sequentially receives the databits detected by the detector 110 and outputs the received data bitswithout alteration. The bit output line 121 is connected to the adders122, 123 and 124, so that the received data bits can be sent by the bitoutput line 121 to the adders 122, 123 and 124.

The plurality of shift registers SO, S1 and S2 are connected in seriesto perform shifting operations complementary to each other.Specifically, if data is input to the third shift register S2, a valueprestored in the third shift register S2 may be shifted to the secondshift register S1 and stored therein, and a value prestored in thesecond shift register S1 may be shifted to the first shift register SOand stored therein complementarily to the above shifting operation.

The first adder 122 sums the data bit value output from the bit outputline 121, the value prestored in the first shift register SO and thevalue prestored in the third shift register S2, and outputs the sum ofthe values to the third shift register S2.

The second adder 123 sums the data bit value output from the bit outputline 121, the value prestored in the second shift register S1 and thevalue prestored in the third shift register S2, and outputs the sum ofthe values as a first encoding value Z for data bit value D.

The third adder 124 sums the data bit value output from the bit outputline 121 and the value prestored in the second shift register S1, andoutputs the sum of the values as a second encoding value Z² for data bitvalue D.

Accordingly, if a single data bit value D is input, the values D, Z¹ andZ² may be simultaneously output by the shift operations of the shiftregisters SO, S1 and S2. The stream constructor 130 constructs a streamby sequentially arranging the output values D, Z¹ and Z².

FIG. 3 is an exemplary diagram explaining a transmission streamprocessing method in the transmission stream processing device of FIG. 1according to an exemplary embodiment of the present invention. In FIG.3, if a single byte comprising data bits DO to D7 (D7 being the mostsignificant bit (MSB) and DO being the least significant bit (LSB)) isinput, the data bits may be detected sequentially from the MSB to theLSB, and the detected bits may be output to the encoder 120 (S310).

The encoder 120 outputs the data bit values, first encoding value andsecond encoding value, in response to the input data bit values (S320).

The stream constructor 130 sequentially arranges the output data bitvalues, first encoding value and second encoding value, and constructs astream comprising three bytes (S330). Specifically, the streamconstructor 130 sequentially arranges initial output data D7, Z¹ ₇ andZ² ₇, from the MSB of the first byte of the stream, and then arrangesnext output data D6, Z¹ ₆ and Z² ₆ sequentially. Subsequently, thestream constructor 130 sequentially arranges D5 and Z¹ ₅ among nextoutput data D5, Z¹ ₅ and Z² ₅, and then arranges Z² ₅ in the MSB of thesecond byte of the stream. Accordingly, a single data bit D and twocorresponding encoding values Z¹ and Z² may be sequentially arranged,and as a result, coding may be performed at a coding rate of ⅓.

FIG. 4 is a block diagram showing a configuration of a transmissionstream processing device according to another exemplary embodiment ofthe present invention. In FIG. 4, the transmission stream processingdevice according to the other exemplary embodiment of the presentinvention comprises a duplicator 210, a detector 220, an encoder 230 anda stream constructor 240.

The duplicator 210 receives a stream, and generates place-holders in aportion of each data bit of the stream. The place-holders are regionsinto which the encoding values are inserted. The duplicator 210 maygenerate two consecutive place-holders for each data bit so that thestream can be coded at a coding rate of ⅓.

Specifically, the duplicator 210 divides each byte of the input streaminto three sections. Some of the bit values and null data (for example,0) for a single byte may be placed in each of the divided bytes. Aregion in which the null data is placed becomes a place-holder.

For example, if a single byte of the stream comprises data bits D7, D6,D5, D4, D3, D2, D1 and DO from the MSB, the duplicator 210 may generatetwo consecutive placeholders for each data bit. In other words, theduplicator 210 may output a first byte comprising D7, 0, 0, D6, 0, 0, D5and 0, a second byte comprising 0, D4, 0, 0, D3, 0, 0 and D2, and athird comprising 0, 0, D1, 0, 0, DO, 0 and 0.

The detector 220 detects only the data bits from the bytes output fromthe duplicator 210, and outputs the detected data bits to the encoder230.

The encoder 230 encodes the detected data bits and outputs two encodingvalues for each data bit.

The stream constructor 240 constructs a stream in such a manner that theencoding values output from the encoder 230 are inserted into theplace-holders generated by the duplicator 210. Consequently, twoencoding values are added to a single data bit, and thus it is possibleto perform coding of the stream at a coding rate of ⅓.

FIG. 5 is a circuit diagram showing a configuration of the encoder 230which is applied to the transmission stream processing device of FIG. 4according to an exemplary embodiment of the present invention. Theencoder 230 of FIG. 5 comprises a plurality of shift registers SO, S1and S2, and a plurality of adders 231, 232 and 233.

The configuration and connection relationships of the plurality of shiftregisters SO, S1 and S2 and plurality of adders 231, 232 and 233 are thesame as those of the plurality of shift registers SO, S1 and S2 andplurality of adders 122, 123 and 124 shown in FIG. 3, so repeateddescription thereof is omitted. The encoder 230 does not include a bitoutput line which outputs input data bits without alteration in theencoder 230 of FIG. 5, and thus the encoder 230 may output only encodingvalues Z¹ and Z², even if data bit D is input.

FIG. 6 is an exemplary view explaining a transmission stream processingmethod in the transmission stream processing device of FIG. 4. In FIG.6, if the data bits are detected from the stream comprising three bytesoutput from the duplicator 210 (S610), the detected data bits may beinput to the encoder 230. Accordingly, the encoder 230 may output thefirst encoding value and second encoding value corresponding to eachdata bit simultaneously (S620).

The stream constructor 240 may construct a stream by inserting theoutput first and second encoding values into the place-holders generatedin one side of each corresponding data bit (S630). Specifically, thestream constructor 240 may sequentially arrange encoding values Z¹ ₇ andZ² ₇ for data bit D7 next to data bit D7 placed in the MSB of the firstbyte. In the same manner, encoding values Z¹ ₆, Z² ₆, Z¹ ₅, Z² ₅, Z¹ ₄,Z² ₄, Z¹ ₃, Z² ₃, Z¹ ₂, Z² ₂, Z¹ ₁, Z² ₁, Z¹ ₀ and Z² ₀ may be insertedinto the place-holders, and thus a stream of three bytes may be formed.

The encoded stream may be transmitted to a digital broadcastingreceiving apparatus through various subsequent processes in the samemanner as described above. Specifically, processing such asrandomization, interleaving, multiplexing of a sync signal, trellisencoding, VSB modulating, upconverting or the like may be performed.

The transmission stream processing devices shown in FIGS. 1 and 4 areapplicable to normal data or turbo coding data. In other words, if amulti-data stream comprising normal data and turbo coding data isgenerated, the generated multi-data stream may be randomized and aparity area may be generated, and then interleaving may be performed.After demultiplexing and detecting only the turbo coding data from themulti-data stream, encoding may be performed in the same manner asdescribed above. Accordingly, the turbo coding data may be processedmore robustly. Subsequently, the encoded turbo coding data may beinterleaved, and then be multiplexed into the multi-data stream again.Therefore, processing such as data deinterleaving, Reed-Solomonencoding, data interleaving, trellis encoding, multiplexing of a syncsignal, modulating, or the like may be performed on the reconstructedmulti-data stream, and the processed multi-data stream may be outputthrough a wireless channel. The above transmission stream processingprocesses are known to those of ordinary skill in the art, so detaileddescription thereof is omitted.

FIG. 7 is a block diagram showing a configuration of a reception streamprocessing device which is applicable to a digital broadcastingreceiving apparatus and which receives the stream encoded by thetransmission stream processing devices of FIGS. 1 and 4.

In FIG. 7, the reception stream processing device comprises a receiver710, a detector 720 and a decoder 730.

The receiver 710 receives a stream coded at a coding rate of ⅓. Thereceiver 710 may comprise a demodulator (not shown) and an equalizer(not shown). The demodulator receives a stream transmitted from thedigital broadcasting receiving apparatus via an antenna and demodulatesthe received stream. The equalizer equalizes the demodulated stream.Accordingly, the receiver 710 may generate a stream having the sameconfiguration as the final streams as shown in FIG. 3 or FIG. 6, and maytransfer the generated stream to the detector 720.

The detector 720 detects data bits and encoding values from the streamreceived by the receiver 710. In other words, the detector 720 maysequentially detect values D, Z¹ and Z² from among the received bytestreams, and may send the detected values to the decoder 730. In thissituation, the detector 720 may correctly detect the encoding valuesusing sync signals output from the digital broadcasting receivingapparatus and position information of the predefined encoding values.The received bytes are respectively divided into every three bytes. Forexample, every three bits from the MSB of the first byte may be divided,and may be output to the decoder 730. In this situation, the remainingbits of the first byte are connected to the MSB of the second byte, andthen the stream of the connected bits may be output to the decoder 730.Accordingly, the data bits and encoding values may be appropriatelyprovided to the decoder 730.

The decoder 730 performs decoding using the detected data bits andencoding values, to restore data in the stream. Accordingly, the datastream comprising the data bits D0 to D7 can be retrieved.

FIG. 8 is a flowchart explaining a reception stream processing methodaccording to another exemplary embodiment of the present invention. InFIG. 8, if the stream coded at a coding rate of ⅓ is received (S810),the data bits and encoding values contained in the received stream maybe detected from the stream (S820). In this situation, two encodingvalues may be detected for each data bit.

Next, decoding may be performed using the detected encoding values anddata bits to restore data (S830). Therefore, it is possible to receiveand process a stream coded at an unusual coding rate, for example acoding rate of ⅓.

As described above, according to the exemplary embodiments of thepresent invention, a stream may be coded and transmitted at a codingrate of ⅓, and the stream may be received and data may be retrieved fromthe received stream. Accordingly, when a multi-transmission stream isgenerated, the type of data may be varied, and thus it is possible toefficiently use the multi-transmission stream.

Although a few exemplary embodiments of the present invention have beenshown and described, it would be appreciated by those skilled in the artthat changes may be made in this embodiment without departing from theprinciples and spirit of the invention, the scope of which is defined inthe claims and their equivalents.

1. A transmission stream processing device comprising: a detector whichdetects data bits in a stream; an encoder which encodes the data bitsdetected by the detector and generates two encoding values for each databit; and a stream constructor which constructs a transmission streamwith a coding rate of ⅓ using the encoding values generated by theencoder.
 2. The transmission stream processing device of claim 1,wherein the encoder comprises: first, second and third shift registerswhich are connected in series and perform shifting operationscomplementary to each other; a bit output line which sequentiallyreceives the data bits detected by the detector and outputs a data bitvalue of each data bit without alteration; a first adder which sums thedata bit value output from the bit output line, a value prestored in thefirst shift register and a value prestored in the third shift register,and outputs the sum to the third shift register; a second adder whichsums the data bit value output from the bit output line, a valueprestored in the second shift register and a value prestored in thethird shift register, and outputs the sum as a first encoding value forthe data bit value; and a third adder which sums the data bit valueoutput from the bit output line and the value prestored in the secondshift register, and outputs the sum as a second encoding value for thedata bit value.
 3. The transmission stream processing device of claim 2,wherein the stream constructor constructs the transmission stream bysequentially arranging the data bit value, first encoding value andsecond encoding value which are output from the encoder.
 4. Thetransmission stream processing device of claim 1, further comprising aduplicator which receives the stream and generates place-holders at oneside of each of the data bits in the stream.
 5. The transmission streamprocessing device of claim 4, wherein the encoder comprises: first,second and third shift registers which are connected in series andperform shifting operations complementary to each other; a first adderwhich sums a data bit value of a data bit detected by the detector, avalue prestored in the first shift register and a value prestored in thethird shift register, and outputs the sum to the third shift register; asecond adder which sums the data bit value, a value prestored in thesecond shift register and a value prestored in the third shift register,and outputs the sum as a first encoding value for the data bit value;and a third adder which sums the data bit value and the value prestoredin the second shift register, and outputs the sum as a second encodingvalue for the data bit value.
 6. The transmission stream processingdevice of claim 5, wherein the stream constructor constructs thetransmission stream by inserting the first and second encoding valuesoutput for each data bit in the place-holders.
 7. A transmission streamprocessing method comprising: detecting data bits in a stream; encodingthe detected data bits to generate two encoding values for each databit; and constructing a transmission stream with a coding rate of ⅓using the encoding values.
 8. The transmission stream processing methodof claim 7, wherein the encoding comprises encoding each of the databits using an encoder which comprises first, second and third shiftregisters, which are connected in series and perform shifting operationscomplementary to each other, and a plurality of adders, and outputs databit values and the two encoding values for each data bit.
 9. Thetransmission stream processing method of claim 8, wherein theconstructing comprises sequentially arranging the data bit value, afirst encoding value and a second encoding value which are output fromthe encoder, to construct the transmission stream.
 10. The transmissionstream processing method of claim 7, further comprising receiving thestream and generating place-holders on one side of each of the data bitsin the stream, wherein the detecting comprises detecting the data bitsin the stream having the place-holders.
 11. The transmission streamprocessing method of claim 10, wherein the encoding comprises encodingeach of the data bits using an encoder which comprises first, second andthird shift registers, which are connected in series and performshifting operations complementary to each other, and a plurality ofadders, and outputs the two encoding values for each data bit.
 12. Thetransmission stream processing method of claim 11, wherein theconstructing comprises constructing the transmission stream by insertingthe two encoding values output from the encoder into the place-holders.13. A reception stream processing device comprising: a receiver whichreceives a stream coded at a coding rate of ⅓; a detector which detectsdata bits and encoding values in the stream; and a decoder whichperforms decoding using the data bits and the encoding values, which aredetected by the detector, to retrieve data in the stream.
 14. Areception stream processing method comprising: receiving a stream codedat a coding rate of ⅓; detecting data bits and encoding values in thestream; and performing decoding using the data bits and the encodingvalues, which are detected, to retrieve data in the stream.
 15. Thereception stream processing apparatus of claim 13, wherein the detectordetects two encoding values for each data bit.
 16. The reception streamprocessing method claim 14, wherein the detecting comprises detectingtwo encoding values for each data bit.